High Speed Signal Propagation

1. The "Big Four" properties govern all high-speed digital transmission lines

Only four properties really affect the performance of most digital transmission structures.

The core parameters. High-speed digital design cuts across multiple orders of magnitude of frequency, power, and physical scale. To navigate this complex landscape, engineers must focus on the "Big Four" properties: characteristic impedance, propagation delay, high-frequency loss, and crosstalk. These properties dictate how cleanly a signal travels from transmitter to receiver, regardless of whether the physical medium is a PCB trace, a coaxial cable, or a rusty barbed-wire fence.

Physical scaling rules. When you scale the physical dimensions of a lossless, distributed circuit by a factor of $k$, its inductances and capacitances scale by $k$, shifting its resonant frequencies by $1/k$. However, scaling the width, height, and thickness of a transmission line by a common factor has no effect on its characteristic impedance or per-unit-length delay. This explains why:

• High-frequency connectors must be made incredibly small to push parasitic resonances out of the signal's bandwidth.
• Widening a trace while keeping its height-to-width ratio constant preserves its impedance.
• Shorter rise times require shorter allowable lengths of unterminated transmission line stubs.

The loop concept. Current always flows in a complete loop, meaning that for every signal current, there must be an equal and opposite return current. At high frequencies, this return current naturally seeks the path of least inductance, which lies directly beneath the signal trace on the reference plane. If this return path is interrupted, the loop area increases, causing severe EMI and crosstalk.

2. High-frequency current crowds the outer surface of conductors due to the skin effect

Magnetic fields within the conductor adjust the distribution of current, forcing it to flow only in a shallow band just underneath the surface of the conductor.

The skin depth. At DC and low frequencies, current flows uniformly through the entire cross-sectional area of a conductor. As frequency rises, the changing magnetic fields inside the conductor induce internal eddy currents that oppose the main current in the center and reinforce it at the outer edges. This forces the current into a shallow outer layer called the skin depth, which shrinks in inverse proportion to the square root of the frequency.

Impact on resistance. This current crowding dramatically increases the AC resistance of the conductor, which rises with the square root of frequency above the skin-effect onset frequency. Simultaneously, the internal inductance of the conductor decreases because magnetic flux can no longer penetrate its interior. This transition from uniform current flow to surface-only flow alters both the resistive and inductive properties of the line, requiring advanced modeling near the transition region.

Proximity and roughness. The skin effect is further complicated by the proximity effect and surface roughness. When two conductors are close together, their mutual magnetic fields pull the current toward the facing surfaces, further concentrating the current and increasing AC resistance. Additionally:

• Surface roughness on a scale of the skin depth forces current to travel a longer, undulating path, increasing loss.
• Nickel plating on copper traces can triple high-frequency losses due to nickel's high magnetic permeability.
• Stranded conductors have a smaller effective skin-effect diameter than solid conductors of the same overall size.

3. Dielectric loss dominates high-frequency attenuation and scales linearly with frequency

As the frequency is increased, however, the skin-effect loss grows only in proportion to the square root of frequency, while the dielectric loss grows at a faster rate in direct proportion to frequency.

The dielectric mechanism. Dielectric loss occurs when the insulating material surrounding a conductor absorbs electromagnetic energy and converts it into heat. This loss is characterized by the dielectric loss tangent ($\tan \theta$), which represents the ratio of in-phase conduction current to quadrature displacement current. Unlike skin-effect loss, which increases with the square root of frequency, dielectric loss increases linearly with frequency, making it the dominant loss mechanism at multi-gigahertz speeds.

Material and mixtures. The choice of PCB substrate material directly determines the high-frequency attenuation of the system. Standard FR-4 has a relatively high loss tangent (0.02), making it unsuitable for long, high-speed runs, whereas exotic materials like PTFE or Rogers have much lower loss tangents. For composite structures like microstrips, the effective dielectric constant is a mixture of the substrate and air:

• Air has a dielectric constant of 1.0 and zero loss, which speeds up microstrip propagation.
• Foaming a dielectric (introducing air bubbles) reduces both the effective dielectric constant and the loss tangent.
• The effective loss tangent of a microstrip is always slightly less than that of a fully embedded stripline.

The causality constraint. Real and imaginary parts of dielectric permittivity are inextricably linked by the Kramers-Kronig relations. A material cannot have a constant loss tangent across all frequencies without its dielectric constant also changing with frequency. This dispersion causes high-frequency components of a digital pulse to travel faster than low-frequency components, leading to signal distortion and a long, slow-settling tail in the step response.

4. Every trace is always a transmission line, requiring proper termination to prevent resonance

A pcb trace of any length always remains a transmission line.

The transmission line. Every electrical connection consists of outgoing and returning signal paths that support wave propagation in both directions. When a trace's propagation delay is short compared to the signal's rise time, we can model it as a lumped-element circuit. However, once the rise time is comparable to or shorter than the line delay, the temporal disconnection between the driver and the load becomes apparent, and the trace must be treated as a distributed transmission line.

The threat of resonance. An unterminated transmission line acts as an open-ended cavity that can store and reflect energy, leading to severe resonance and ringing. This resonance occurs at odd multiples of the quarter-wave frequency and can amplify noise to the point of causing spurious switching. To prevent this, engineers must use termination strategies to absorb the propagating energy:

• Source termination: A resistor placed at the driver matches the line impedance, absorbing reflections on their return trip.
• End termination: A resistor placed at the load matches the line impedance, absorbing the wave on its first arrival.
• Both-ends termination: Resistors at both ends provide maximum immunity to reflections from intermediate discontinuities.

The impedance matching. To achieve first-incident-wave switching, the termination resistance must match the characteristic impedance of the line. In the LC region, this impedance is a flat, real value ($Z_0 = \sqrt{L/C}$). However, in the RC region (at low frequencies or on highly resistive lines), the characteristic impedance is complex and varies with the inverse square root of frequency, making perfect termination extremely difficult.

5. Differential signaling defeats ground bounce and common-mode noise through symmetry, not tight coupling

Differential signaling defeats ground bounce.

The power of symmetry. Single-ended signaling relies on a shared, low-impedance reference plane to carry return currents, making it highly vulnerable to ground bounce and common-mode noise. Differential signaling solves this by transmitting two complementary signals (+ and -) on a pair of matched traces. Because the signals are equal and opposite, their return currents cancel each other out in the reference plane, and any external noise that affects both traces equally is rejected by the differential receiver.

The coupling misconception. A common misconception is that differential traces must be tightly coupled to work effectively. In reality, the primary benefits of differential signaling—common-mode rejection and ground-bounce immunity—depend on the symmetry of the traces and the balance of the driver, not on their proximity. Squeezing traces together actually lowers their differential impedance, forcing you to use narrower, more resistive traces that suffer from higher skin-effect losses.

Managing skew. The most critical requirement for a differential pair is that the two signals arrive at the receiver at exactly the same time. Any difference in arrival time, known as intra-pair skew, converts a portion of the differential signal into a common-mode signal, which increases electromagnetic emissions and reduces noise margin. To minimize skew:

• Match the physical lengths of the two traces to within 1/20 of the signal rise time.
• Avoid routing differential pairs over splits or gaps in the underlying reference planes.
• Balance the number of left-hand and right-hand turns to naturally cancel out corner-induced skew.

6. Vias and physical discontinuities act as parasitic lumped-element capacitors or inductors

A small lumped-element capacitance shunting a transmission line creates a backwards-propagating reflection.

Discontinuities as parasitics. Physical features like vias, connector pins, and component pads interrupt the uniform cross section of a transmission line. When a high-speed signal encounters these features, they act as parasitic lumped-element capacitors or inductors. A via, for example, adds excess capacitance due to its pads and the proximity of the reference planes, while the vertical barrel of the via adds series inductance.

The reflection penalty. These parasitic elements generate backwards-propagating reflections that degrade the rising edge of the forward-propagating signal. The peak amplitude of the reflection is proportional to the ratio of the parasitic impedance to the signal rise time. If the rise time is very fast, even a tiny via can create a significant reflection that disrupts first-incident-wave switching.

Mitigation and compensation. Engineers can minimize the impact of these parasitic discontinuities through careful layout and compensation techniques:

• Pothole compensation: Narrowing the trace width (increasing inductance) on either side of a capacitive via can cancel out its excess capacitance.
• Back-drilling: Drilling out the unused, dangling portion of a through-hole via eliminates the resonant stub and reduces capacitance.
• Pad stripping: Removing unused pads on inner layers of a via reduces its parasitic capacitance to the surrounding planes.

7. Clock distribution demands absolute monotonicity, low skew, and low jitter

Because they are so fast, so heavily loaded, and so important for system timing, clock signals are subject to special requirements that may not apply to other signals.

The clock's unique role. The clock is the most critical signal in a synchronous digital system, regulating the timing of every flip-flop. Unlike data signals, which only need to be stable at the sampling instant, a clock is an asynchronous trigger. Any non-monotonic behavior, such as a glitch or ringback within the receiver's switching threshold, can cause double-clocking and catastrophic system failure.

The battle against skew. Clock skew is the difference in arrival times of the clock signal at different destination registers. Skew directly subtracts from the available setup and hold times, limiting the maximum operating frequency of the system. To minimize skew, designers must build balanced clock trees using low-skew repeaters and equal-length, identically loaded transmission lines:

• Zero-delay buffers: Use PLL or DLL feedback loops to align the output clock edges precisely with the input reference clock.
• Equal loading: Place identical capacitive loads and terminations on every branch of the clock tree.
• Avoid mixing layers: Do not route some clock lines as fast microstrips and others as slower striplines.

Controlling clock jitter. Clock jitter is the short-term variation of the clock edge from its ideal position, caused by power supply noise, crosstalk, and thermal noise. Jitter is particularly dangerous when the clock is used as a reference for a PLL, as the PLL can amplify high-frequency jitter. To prevent this, clock sources must be provided with dedicated, heavily filtered power supplies and routed far away from noisy data lines.

8. Frequency-domain simulation (FFT) is the most efficient way to model complex, lossy transmission lines

When the number of simulated cable sections in the time-step method becomes large, the FFT-based approach computes much more rapidly.

The simulation challenge. Simulating high-speed digital signals on long, lossy transmission lines is computationally expensive. Time-domain simulators like SPICE must segment the line into thousands of tiny sections, solving the circuit equations iteratively at each time step. This approach becomes painfully slow when the propagation delay of the line is much larger than the rise time of the signal.

The FFT advantage. Frequency-domain simulation solves this problem by converting the time-domain excitation signal into the frequency domain using a Fast Fourier Transform (FFT). In the frequency domain, the complex, frequency-dependent losses of the transmission line (like skin effect and dielectric loss) are represented by simple algebraic multiplications. The resulting frequency-domain response is then converted back to the time domain using an inverse FFT.

Causality and accuracy. The FFT method is highly accurate and guarantees a real, causal, minimum-phase response, provided that the real and imaginary parts of the transfer function are properly matched. It is particularly useful for:

• Simulating long backplane traces and cables with complex, frequency-varying losses.
• Evaluating the eye-opening and intersymbol interference of long, random data sequences.
• Optimizing transmitter pre-emphasis and receiver equalization networks.

9. Power and ground planes are distributed systems prone to high-frequency resonance

With 200 psec rise/fall times, the drivers perceive the power-and-ground structure as a distributed object with a significant delay.

The distributed plane. In low-speed designs, the power and ground planes behave like a large, lumped-element capacitor that provides a low-impedance path for bypass currents. However, at high speeds, where the signal rise time is shorter than the propagation delay across the board, the planes behave as a distributed parallel-plate waveguide.

The threat of resonance. When a high-speed driver switches, it injects a transient current wave into the power-ground cavity. This wave propagates outward, reflects off the open edges of the board, and travels back, creating standing-wave resonances. These resonances cause the power supply voltage to fluctuate wildly across the board, leading to:

• Increased electromagnetic emissions (EMI) as the board edges act as slot antennas.
• Spurious noise coupled into quiet signal lines through their reference planes.
• Jitter in sensitive clock circuits and PLLs.

Damping the planes. To control power-plane resonance, designers must place decoupling capacitors strategically across the board. These capacitors act as local reservoirs of charge, damping the high-frequency waves before they can reflect off the board edges. Additionally, using thin dielectric layers between the power and ground planes increases the natural capacitive coupling and provides significant distributed resistive damping.